Currently, handling of data packets of arbitrarily packetized data received from a generic I/O adapter by, for example, a virtualization router can be inefficient since the router must perform address translation prior to storing the data to system memory. A problem can arise because the generic I/O adapter functions without regard for system cache-line boundaries, resulting in a likelihood of forwarded packets being misaligned, which can in turn cause the virtualization router to perform inefficiently. In particular, address translation is often employed with I/O, for example, when virtualizing I/O adapters. Modern I/O adapters attempt to optimize performance by aligning storage requests at cache-line sizes on cache-line boundaries. However, if the address translation takes place outside of the adapter, it is likely that the accesses will be misaligned with the target system's cache-line boundaries. The resulting misalignment can cause significant performance degradation.